1. Field of the Invention
The present invention relates to a matched filter to be used in synchronous acquisition or the like in wireless communication, and, more particularly, to a matched filter whose circuit scale can be reduced considerably.
2. Description of the Related Art
[Conventional Matched Filter (1): FIG. 13]
A conventional matched filter will be described referring to FIG. 13. FIG. 13 is a configurational diagram showing one example of a conventional matched filter.
As shown in FIG. 13, in a case of 8× oversampling for 512 chips, for example, a conventional matched filter includes, for each of an I component (in-phase component) and a Q component (orthogonal component) of a received signal orthogonally detected and 8×-oversampled, a matched filter circuit section having 512×8 FFs (Flip Flops) 31, multipliers 32 equal in number to the FFs 31, and an accumulating section 33, and a √(I2+Q2) calculating section 34. Although the configuration of the matched filter circuit for the Q component is not shown, it is the same as that for the I component.
Each FF 31 holds an input sample for one sample time, and then outputs the sample.
Each multiplier 32 performs despreading by multiplying a sample output from an associated FF 31 by a set spread code. The spread code corresponds to an associated chip.
The accumulating section 33 adds up all the outputs of the multipliers 32.
The √(I2+Q2) calculating section 34 calculates correlation value data by performing an operation √(I2+Q2) based on values output from the accumulating section 33 for the I component and the accumulating section for the Q component.
In the matched filter with the foregoing configuration, for each of the I component and Q component, the FFs 31 hold samples at every sample timing, the multipliers 32 perform despreading by multiplying the held samples by spread codes for the respective chips, the accumulating section 33 adds up all the outputs of the multipliers 32, and the √(I2+Q2) calculating section 34 calculates and outputs correlation value data at every sample time. Then, synchronous acquisition is carried out based on the correlation value data output from the matched filter.
However, the conventional matched filter with the foregoing configuration takes a structure of spread symbol length×oversampled taps, thus undesirably increasing the circuit scale.
[Conventional Matched Filter (2): FIG. 14]
There is a matched filter intended to reduce the circuit scale (second conventional matched filter). The second conventional matched filter will be described referring to FIG. 14. FIG. 14 is a configurational diagram the configuration of the second conventional matched filter.
As shown in FIG. 14, for each of an I component and a Q component, the second conventional matched filter includes a moving average filter (N=8) 35, FFs 31 separated into 512 blocks each containing eight FFs 31, multipliers 32 each provided for eight FFs 31, an accumulating section 33 and a √(I2+Q2) calculating section 34.
The moving average filter (N=8) 35 outputs a moving average which is an average of data of eight samples.
Each multiplier 32 performs despreading by multiplying a moving average, output for every eight FFs 31, by a spread code corresponding to an associated chip.
The FF 31, the accumulating section 33 and the √(I2+Q2) calculating section 34 will not be described for their structures are the same as those of the first conventional matched filter (1).
In the second conventional matched filter, for each of an I component and a Q component, the moving average filter (N=8) 35 outputs a moving average for every eight samples, each FF 31 holds the moving average at every sample timing, each multiplier 32 performs despreading by multiplying the moving average by the spread code for each block (for every eight moving averages), the accumulating section 33 adds up all the multiplication results, and the √(I2+Q2) calculating section 34 calculates and outputs correlation value data at every sample time.
Because the second conventional matched filter performs despreading every eight moving averages each for eight samples, the number of the multipliers can be ⅛ of the number of the FFs 31 and can thus be reduced to ⅛ of the number of the FFs 31 of the first conventional matched filter as shown in FIG. 13.
[Documents on Related Arts]
Related arts on a matched filter are disclosed in Japanese Patent Application Laid-Open No. H09-080163 (Patent Document 1), Japanese Patent Application Laid-Open No. H09-116522 (Patent Document 2), Japanese Patent Application Laid-Open No. H11-196067 (Patent Document 3), and Japanese Patent Application Laid-Open No. H11-225093 (Patent Document 4).
Patent Document 1 describes the configuration of a system which uses a matched filter and performs a sampling process using a dual-port RAM.
However, Patent Document 1 does not reduce the circuit scale in the despreading process employing specific ways of writing and reading data to and from the dual-port RAM.
Patent Document 2 describes the configuration of a matched filter which performs a sample/hold process selectively using two RAMs.
Patent Document 3 describes the configuration of a matched filter which detects a delay path using a plurality of registers in a sample/hold process.
Patent Document 4 describes the configuration of a matched filter which receives signals using a plurality of registers in a sample/hold process.
However, none of the configurations in Patent Documents 2 to 4 use a dual-port RAM.
[Patent Document 1] Japanese Patent Application Laid-Open No. H09-080163
[Patent Document 2] Japanese Patent Application Laid-Open No. H09-116522
[Patent Document 3] Japanese Patent Application Laid-Open No. H11-196067
[Patent Document 4] Japanese Patent Application Laid-Open No. H11-225093
To improve the timing precision for synchronous acquisition, however, the conventional matched filters suffer an increase in the circuit scale due to an increased number of taps. In addition, the second conventional matched filter which performs a separation process cannot use a dual-port RAM.